Many modern microprocessors include virtual memory capability, and in particular, a memory paging mechanism. As is well known in the art, the operating system creates page tables that it stores in system memory that are used to translate virtual addresses into physical addresses. The page tables may be arranged in a hierarchical fashion, such as according to the well-known scheme employed by x86 architecture processors as described in Chapter 3 of the IA-32 Intel Architecture Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, June 2006, which is hereby incorporated by reference in its entirety for all purposes. In particular, page tables include page table entries (PTE), each of which stores a physical page address of a physical memory page and attributes of the physical memory page. The process of taking a virtual memory page address and using it to traverse the page table hierarchy to finally obtain the PTE associated with the virtual address in order to translate the virtual address to a physical address is commonly referred to as a tablewalk.
Because the latency of a physical memory access is relatively slow, the tablewalk is a relatively costly operation since it involves potentially multiple accesses to physical memory. To avoid incurring the time associated with a tablewalk, processors commonly include a translation lookaside buffer (TLB) that caches the virtual to physical address translations. However, the size of the TLB is finite, and when a TLB miss occurs, the tablewalk must be incurred. Therefore, what is needed is a way to reduce the time required to perform a page table walk.